The invention relates to testing integrated circuits, and, more particularly, to a method and apparatus for measuring jitter in phase locked loops.
Phase locked loops (PLLs) have been used for clock generation in microprocessors. One advantage to using a PLL is the multiplication of the reference clock frequency. The PLL can generate an output clock or multiple output clocks, that are a multiple of the reference clock frequency, with each of the PLL clocks being phase aligned.
The advantages of a PLL become lost if the PLL experiences xe2x80x9cjitterxe2x80x9d or variation of the phase alignment. Thus, there exist test methods to detect the presence of PLL jitter. PLL jitter is often measured deterministically, finding a distribution of jitter and computing the standard deviation to obtain a 3 sigma jitter number. While this is an acceptable test method for most specifications, a single PLL phase variation event can cripple high speed integrated circuits. Thus, there is a need for an absolute measurement of PLL jitter rather than a statistical one.
An exemplary embodiment of the invention is a method for evaluating jitter of a phase locked loop circuit generating a phase locked loop output signal. The method includes generating a test initiate signal and generating a trigger signal in response to the test initiate signal. The trigger signal is synchronized with the phase locked loop output signal. A disturbance signal is generated to induce jitter in the phase locked loop output signal. The jitter in the phase locked loop output signal is then evaluated.